The present disclosure relates to semiconductor devices. When a non-volatile semiconductor memory device is manufactured, a channel hole may be formed through insulation layers and sacrificial layers that are alternately and repeatedly stacked on a substrate. A semiconductor pattern may be formed in a lower portion of the channel hole. An Oxide-Nitride-Oxide (ONO) layer and a channel may be formed in an upper portion of the semiconductor pattern. An opening may be formed through the insulation layers and the sacrificial layers, and the sacrificial layers exposed by the opening may be removed to form gaps exposing sidewalls of the ONO layer and the semiconductor pattern. Gate electrodes may be formed to fill the gaps.
Controlling breakdown voltages of word lines and String Select/Selection Lines (SSLs), which may be formed at relatively high (e.g., upper) levels among the gate electrodes, may be possible because the ONO layer may be formed between the word lines and the channel, and between the SSLs and the channel. Controlling breakdown voltages of Ground Select/Selection Lines (GSLs), however, which may be formed at relatively low (e.g., lower) levels among the gate electrodes, may be more difficult because the GSLs may directly contact the semiconductor pattern.